As the integration densities of semiconductor devices continue to increase, the widths of gate electrodes are generally reduced. As the width of a conventional doped polysilicon gate electrode approaches 0.25 microns (.mu.m), however, its performance may deteriorate. In particular, as the resistance of the polysilicon gate increases with the reduction of the width, the transmission of a gate signal may thus be delayed. Furthermore, when a sufficiently narrow polysilicon gate is used in a p-MOS transistor, short channel effects may increase because of the buried channel formed to lower the threshold voltage.
In order to reduce the effects of the above mentioned problems, the formation of gate electrodes from a conductive material having a relatively low resistivity and a work function corresponding to the midgap of silicon have been investigated. In particular, it has ben noted that a polycide structure formed from a silicide (a compound formed of metal and silicon which are heat-treated) and polysilicon can be used as a gate electrode material in place of a doped polysilicon structure.
The polycide structure can include tungsten silicide (WSi.sub.x) or titanium silicide (TiSi.sub.x) as the silicide. Alternately, a silicide including a metal having a relatively high melting point, such as a cobalt silicide (CoSi.sub.x) for example, can be used. Of the above mentioned silicides, titanium silicide (hereinafter referred to as TiSi.sub.x) excels in thermal stability and has a relatively low resistivity which is about one quarter that of tungsten silicide (WSi.sub.x). TiSi.sub.x is thus considered a very suitable material for a gate electrode, and in particular for a gate electrode for a device such as a dynamic random access memory (DRAM) with a memory capacity of over 1 gigabit. The use of titanium silicide (TiSi.sub.x) in a gate electrode can provide improved transistor operation due to its relatively low resistivity and the midgap work function of silicon.
The titanium silicide and polysilicon layers which make up the gate pattern can be etched using a dry etching technique. In particular, a fluorine-series gas (e.g., sulfur hexafluoride SF.sub.6 or carbon tetrafluoride CF.sub.4), a chlorine-series gas (e.g., hydrogen chloride HCl, chlorine gas Cl.sub.2 or boron trichloride BCl.sub.3), and/or hydrogen bromide HBr can be used as the etching gas. The TiSi.sub.x layer and the polysilicon layer, however, may be susceptible to sidewall erosion during the etch. This sidewall erosion of the gate structure may cause a bridge to form between conductive layers due to a stringer phenomenon wherein a conductive material remains at the eroded portion after the next processing step (e.g., a pad electrode formation step). The reliability of the semiconductor device may thus be decreased and product yield reduced.
The gate oxide layer may also be damaged because fluorine-series gasses and boron trichloride (BCl.sub.3) have low etching selectivities with respect to the oxide. In addition, when hydrogen bromine (HBr) is used as the etching gas, it may react with the TiSi.sub.x layer 8 to produce a significant amount of polymer (i.e., a non-volatile residue) which may remain between the gate electrodes being patterned making it difficult to adjust the critical dimension thereof. Furthermore, when only chlorine gas (Cl.sub.2) is used as the etching gas with a hard mask instead of photoresist, severe sidewall erosion may occur.
FIG. 1 is a scanning electron microscope (SEM) photograph of a titanium silicide (TiSi.sub.x) layer which has been etched using only chlorine gas (Cl.sub.2). As shown, the titanium silicide layer and the underlying polysilicon layer may be undesirably eroded along sidewalls thereof. When etching a polycide layer, the etching mask can be a silicon nitride layer deposited using a low pressure chemical vapor deposition at a temperature of approximately 700.degree. C. or a silicon nitride layer deposited using plasma-enhanced chemical vapor deposition at a temperature of approximately 400.degree. C.
Improved sheet resistance can be provided when using a LPCVD nitride layer etching mask as opposed to a PECVD nitride layer etching mask. As shown in the SEM photograph of FIG. 2, however, a residue may remain in the open regions after the polycide film has been etched using the LPCVD nitride layer etching mask. This residue may be caused by segregation of extra silicon (Si) when heat is applied to a silicide layer. When a PECVD nitride layer etching mask is used, the etching residue may be reduced. A polymer, however, may be generated along sidewalls of the gate pattern during a subsequent self-aligned contact (SAC) step. This polymer can increase the sheet resistance of the gate when compared with gates formed using LPCVD nitride layer etching masks.
Notwithstanding the methods discussed above, there continues to exist a need in the art for improved methods of forming gate structures.